The present invention relates to a temperature compensated crystal oscillator (TCXO).
Recent advances in IC technology and related technology promote size reduction and cost reduction in equipment for mobile communication such as devices or telephone sets for portable, mobile and cordless telephone systems. This progress increases the number of subscribers and users of the radio communication systems, and the carrier frequency spacing (12.5 KHz, for example) and the modulation band width (5 KHz, for example) are decreased. Therefore, a source of oscillation frequency is required to fulfill a severe requirement of the frequency stability. For example, the frequency stability must be equal to or lower than 1 ppm; EQU .vertline..DELTA.f/f.vertline..ltoreq.1 ppm. (1-1)
There is known a digital temperature compensated crystal oscillator (DTCXO) capable of satisfying the requirement of the expression (1-1) in a wide temperature range of -40.degree. C..about.85.degree. C.
FIG. 7 shows a conventional DTCXO system which includes a temperature to voltage coverting circuit 10 for sensing an ambient temperature of a crystal unit 19 and producing an analog temperature voltage Vt representing the sensed temperature, and an analog to digital converter (ADC) circuit 11 for converting the analog voltage signal Vt to a digital temperature data signal T. For example, the digital temperature data signal T is a 10 bit signal. This temperature data signal T is supplied to a memory and operation circuit 12 comprising devices such as E.sup.2 PROM and logic array. The memory and operation circuit 12 stores a collection of compensation data items V (10 bit data, for example) for the temperature compensation of the crystal unit 19. The compensation data item V corresponding to the temperature data T is obtained directly or through a converting operation, and outputted through a register (not shown) as a digital compensation data signal V1. This signal V1 is inputted to a digital to analog converter (DAC) circuit 13 and converted into a analog voltage signal Vcw. The analog voltage signal Vcw is sent from the digital to analog converter circuit 13 to a sample hold and low pass filter circuit 14, in which the analog voltage signal Vcw first undergoes a sample and hold operation, and then is smoothed by a low pass filter (LPF) having a proper time constant (5 ms, for example). The smoothed signal is outputted as a control voltage Vc from the sample hold and low pass filter circuit 14. The control voltage Vc is supplied to a voltage to capacitance converting circuit 15 comprising a variable capacitor, a resistor and a semiconductor switch, etc. The voltage to capacitance converting circuit 15 provides, between output terminals 15A and 15B, an equivalent capacitance Cc corresponding to the control voltage Vc in a manner of one-to-one linear correspondence.
An inverting amplifier 16 is composed of a semiconductor amplifier having a MOS transistor, for example. The inverting amplifier 16 forms a crystal oscillator circuit with the crystal oscillator unit 19 and the equivalent capacitance Cc across the output terminals 15A and 15B of the voltage to capacitance converting circuit 15. The capacitance Cc is connected in series (or in parallel) with the crystal unit 19. Thus, the inverting amplifier 16 performs the temperature compensation by using the capacitance Cc varying in accordance with the temperature, and provides, at an output terminal 16A, a constant frequency signal voltage independent of changes in the ambient temperature.
An auxiliary circuit 17 is a circuit having sub-functions common to the above-mentioned circuits. The auxiliary circuit 17 performs the following functions.
The auxiliary circuit 17 gets an external power supply from an input terminal 17A and directly supplies a voltage, a voltage reference, as a regulator, to each of the above mentioned circuits. The auxiliary circuit 17 enables data writing and reading operations to and from E.sup.2 PROM through an interface terminal 17B, and performs a switching operation between a run mode and a test mode. Furthermore, the auxiliary circuit 17 functions to control the starting operation, and to control the compensation timing.
The above-mentioned circuits are integrated in a one chip LSI 18, as shown in FIG. 7. The resulting small sized DTCXO can provide the temperature compensation of .+-.1 ppm or less by using a crystal unit varying by 15 ppm, for example, in a wide temperature range.
As the demand in the mobile communication system for small size, light weight, low power consumption and low cost grows especially for portable devices, the DTCXO attracts more attention. In addition to the above-mentioned crystal unit 19 and the one chip LSI 18, the DTCXO includes two to four small chip capacitors for the filter of the sample hold and low pass filter circuit 14 and the voltage stabilization of the auxiliary circuit 17. These components are assembled in a package having interconnections and electrode pads (such as 16A, 17A and 17B shown in FIG. 7) for connection with external devices. All these components are improved to reduce the size, power consumption and cost individually or in combination. However, the improvement in the one chip LSI is most effective. The one chip LSI 18 includes both analog circuit components and digital circuit components. Therefore, the LSI layout design must be made small to lessen noise coupling among inner circuit components. Furthermore, the fabrication process is required to be continuous. Therefore, it is not easy to accomplish the object of reducing the size and cost.
FIGS. 8 and 9 show a conventional ADC circuit 11 and a conventional DAC circuit 13.
The ADC circuit 11 shown in FIG. 8 includes a bias generating circuit 20 for generating a bias 2.multidot.VB (VB is a base voltage temperature correction of Vt), a dual slope integration circuit 21, a comparator 22 and an output section 23 comprising a clock, a control circuit for controlling switches SW2j (where j is 1, 2 or 3), a down counter and its register. The T data signal is obtained at the output of the section 23. The control circuit in the section 23 is connected, as shown at 23A, with the switches SW2j.
The bias generating circuit 20 comprises an operational amplifier OP1, a transistor TR and resistors R and R4. The operational amplifier OP1 has a plus input terminal receiving VB, a minus input terminal receiving the voltage Vt from the temperature to voltage converting circuit 10, and an output terminal delivering a biased voltage (2VB-Vt). This biased voltage is supplied to a plus input terminal of the comparator 22. The dual slope integration circuit 21 has a series arrangement of three resistors R21, R22 and R23 connected across a regulated power supply for providing fractional voltages V21 and V22 by these three resistors, an operational amplifier OP2 having a minus input terminal receiving the fractional voltage V21 from a branch point between the resistors R21 and R22 through a series combination of semiconductor switches SW21 and SW22, and a plus input terminal receiving the fractional voltage V22 directly from a branch point between the resistors R22 and R23, a capacitor C21 provided between a branch point between the semiconductor switches SW21 and SW22 and the ground, and a parallel circuit of a capacitor C22 and a semiconductor switch SW23 connected between the minus input terminal and output terminal of the operational amplifier OP2.
The DAC circuit 13 shown in FIG. 9 has a dual slope integration circuit 31 having the same construction as the dual slope integration circuit 21 of the ADC circuit 11 shown in FIG. 8, a semiconductor switch 32 disposed in a path for supplying the output of the integration circuit 31 to the sample hold and low pass filter circuit 14 and a register, counter and gate control circuit 33 which is connected by one or more lines 33A with the switches SW3j.
The integration circuits of the ADC circuit 11 and the DAC circuit 13 are of the double integration type, which can significantly contribute to the size reduction by reducing the numbers of semiconductor switches, resistors and capacitors. However, the following inequality (1-2) exists in general between both circuits though the T data of the ADC circuit 11 and the V1 data of the DAC circuit 13 are identical in word length (10 bits, for example). EQU (2VB-Vt).sub.(max) .noteq.Vcw.sub.(max) ( 1-2)
Therefore: EQU V24.noteq.V34 (1-3)
As a result, both circuits require different capacitors and resistors as follows: EQU C2j.noteq.C3j, R2j.noteq.R3j (1-4)
Furthermore, the LSI configuration of the dual slope integration circuits poses the following three problems.
(i) When each of the temperature data T and the V1 data is 10-bit data, the relationship between the capacitors Ci2 and Ci1 (where i is 2 or 3) is given by: EQU Ci2/Ci1.apprxeq.1025.times.Vi3/Vi4.sub.(max) ( 1-5) PA1 (ii) Since a low resistance switch is difficult to obtain for the size reduction of LSI, the time .tau. for a single OFF-ON-OFF cycle of the semiconductor switch SWij is long, and moreover the semiconductor switches SWi1 and SWi2 are operated alternately. Therefore, the integration time becomes equal to or longer than 2050 .tau. when the T data and V1 data are 10 bits. Assuming .tau.=0.1 ms, the integration time is as long as 205 ms. PA1 (iii) Because of a synergistic effect produced by a combination of the factors mentioned in (i) and (ii) above, the system becomes more susceptible to noise, and the ADC and DAC circuits become less reliable. PA1 a crystal oscillating section which comprises a crystal unit; PA1 a temperature to voltage converting circuit for sensing an ambient temperature of said crystal unit and outputting an analog temperature voltage signal representing a sensed ambient temperature; PA1 a memory and operation circuit for storing a collection of temperature compensation data items, receiving a digital temperature data signal as an input signal, providing a selected data item identified by said digital temperature signal, and producing a digital compensation data signal in accordance with said selected data item; and PA1 a data conversion circuit for producing said digital temperature data signal in accordance with said analog temperature voltage signal from said temperature to voltage converting circuit, and for producing an analog compensation voltage signal in accordance with said digital compensation data signal from said memory and operation circuit, said data conversion circuit comprising a first section for producing an analog intermediate signal, a second section for producing said digital temperature data signal by converting said analog temperature voltage signal in accordance with said analog intermediate signal and delivering said digital temperature data signal to said memory and operation circuit, and a third section for producing said analog compensation voltage signal by converting said digital compensation data signal through said first section. PA1 a crystal unit having a first end and a second end which is connected to a ground; PA1 a MOS transistor comprising a drain, a source and a gate which is connected to said first end of said crystal unit; PA1 a gate voltage fixing resistor connected between the drain and gate of the MOS transistor; PA1 a source resistor connected between the source of the MOS transistor and the ground; PA1 a series circuit of a detecting capacitor and a feedback semiconductor capacitor constituting a Colpitts oscillator circuit; and PA1 a decoupling capacitor connected between the source of the MOS transistor and a node between the detecting and feedback capacitors.
In the expression (1-5), the capacitor Ci2 can not be increased for the size reduction of the LSI, and accordingly, the capacitor Ci2 is set at 100 pF, for example. In this case, Ci1 is equal to or smaller than 1 pF when (Vi3/Vi4.sub.(max))=0.1. With such a small capacitance, the system is readily affected by noise.